View SI51210_4688783.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary rev. 0.7 1/12 copyright ? 2012 by silicon laboratories SI51210 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI51210 t wo o utputs f actory p rogrammable c lock g enerator features applications description the factory programmable SI51210 is industry?s lowest power, smallest footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. the device operates fr om a single crystal or an external clock source and generates 1 to 2 outputs up to 200 mhz. they are factory programmed to provide custom ized output frequencies, control inputs and ac parameter tuning lik e output drive strength that are optimized for customer board cond ition and application requirements. functional block diagram ? generates up to 2 cmos clock outputs from 3 to 200 mhz ? accepts crystal or reference clock input ?? 3 to 166 mhz reference clock input ?? 8 to 48 mhz crystal input ? programmable fsel, ssel, sson , pd , and oe input functions ? low power dissipation ? 2.5 to 3.3 v voltage supply range ? 0.25% to 1.0% spread spectrum (center spread) ? low cycle-cycle jitter ? programmable output rise and fall times ? ultra small 6-pin tdfn package (1.2 mm x 1.4 mm) ? crystal/xo replacement ? emi reduction ? portable devices ? digital still camera ? ip phone ? smart meter 3 2 1 6 4 5 to pin 4 and pin 5 to core programmable configuration register pll with modulation control buffers, dividers, and switch matrix ssclk1/ refclk/ 0e2/fsel/ ssel/ss0n ssclk2/ refclk_d 0e1/fsel/ ssel/ss0n/pd xin/ clkin xout vdd vss v-reg patents pending ordering information: see page 9. pin assignments 6 5 4 1 2 3 vss ssclk2/refclk_d fsel/ssel/sson/ pd/oe1 ssclk1/refclk fsel/ssel/sson/ oe2 vdd xout xin/clkin SI51210
SI51210 2 preliminary rev. 0.7
SI51210 preliminary rev. 0.7 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.2. comments and recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1. input frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2. output frequency range and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3. programmable modulation frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4. programmable spread percent (%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.5. sson or frequency select (fsel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.6. power down (pd ) or output enable (oe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. pin descriptions: 6-pin tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6. package outline (6-pin tdfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
SI51210 4 preliminary rev. 0.7 1. electrical specifications table 1. dc electrical specifications (v dd = 2.5 v 5%, or v dd = 3.3 v 10%, t a = 0 to 70 o c) parameter symbol test condition min typ max unit operating voltage v dd v dd =3.3 v 10% 2.97 3.3 3.63 v v dd =2.5 v 5% 2.375 2.5 2.625 v output high voltage v oh i oh =?4 ma v dd ?0.5 ? ? v output low voltage v ol i ol =4 ma ? ? 0.3 v input high voltage v ih cmos level 0.7 v dd ??v input low voltage v il cmos level 0 ? 0.3 v dd v operating supply current i dd f in =12 mhz, ssclk1 =12 mhz, ssclk2 =24 mhz, c l =0, v dd =3.3 v ?4.5?ma nominal output impedance z o ?30? ? internal pull-up/pull-down resistor r pup /r pd pin 5 ? 150k ? ? input pin capacitance c in input pin capacitance ? 3 5 pf load capacitance c l clock outputs < 166 mhz ? ? 15 pf clock outputs > 166 mhz ? ? 10 pf
SI51210 preliminary rev. 0.7 5 table 2. ac electrical specifications (v dd =2.5v 5%, or v dd =3.3v 10%, t a = 0 to 70 o c) parameter symbol condition min typ max unit input frequency range f in1 crystal input 8 ? 48 mhz input frequency range f in2 reference clock input 3 ? 166 mhz output frequency range f out ssclk1/2, cl=15 pf 3 ? 200 mhz frequency accuracy f acc configuration dependent ? 0 ? ppm output duty cycle dc out measured at v dd /2 45 50 55 % input duty cycle dc in clkin, clkout through pll 30 50 70 % output rise time t r c l =15 pf, 20 to 80% ? 1 3.0 ns output fall time t f c l =15 pf, 20 to 80% ? 1 3.0 ns period jitter pj 1 ssclk1/2, two clocks running, v dd =3.3 v, c l =15 pf ? 150 * ?ps cycle-to-cycle jitter ccj 1 ssclk1/2, two clocks running, v dd =3.3 v, c l =15 pf ? 100 * ?ps power-up time t pu time from 0.9 v dd to valid frequencies at all clock outputs ?1.25.0ms output enable time t oe time from oe raising edge to active at output ssclk (asynchronous) ?15?ns output disable time t od time from oe falling edge to active at output ssclk (asynchronous) ?15?ns *note: jitter performance depends on config uration and programming parameters. table 3. absolute maximum conditions parameter symbol condition min typ max unit main supply voltage v dd ?0.5 ? 4.2 v input voltage v in relative to v ss ?0.5 ? v dd +0.5 v temperature, t s non-functional ?65 ? 150 c temperature, operating ambient t a functional, c-grade 0 ? 70 c esd protection (human body model) esd hbm jedec (jesd 22-a114) ?4000 ? 4000 v esd protection (charge device model) esd cdm jedec (jesd 22-c101) ?1500 ? 1500 v esd protection (machine model) esd mm jedec (jesd 22-a115) ?200 ? 200 v moisture sensitivity le vel msl jedec (j-std-020) 1 note: while using multiple power supplies, the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required .
SI51210 6 preliminary rev. 0.7 2. design considerations 2.1. typical appl ication schematic 2.2. comments and recommendations decoupling capacitor: a decoupling capacitor of 0.1 f must be used between vdd and vss on pin 1. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible. do not use vias between the decoupling capacitor and the vdd pin. in addition, a 10 f capacitor should be placed between vdd and vss. series termination resistor : a series termination resistor is recommended if the distance between the outputs (ssclk or refclk pins) and the load is over 1 ? in ches. the nominal impedance of the ssclk output is about 30 ? . use a 20 ? resistor in series with t he output to terminate a 50 ? trace impedance and place a 20 ? resistor as close to the ssclk output as possible. crystal and crystal load: only use a parallel resonant fundamental at cut crystal. do not use higher overtone crystals. to meet the crystal initial accuracy specification (in ppm) make sure that exter nal crystal load capacitor is matched to crystal load specification. to determi ne the value of cl1 and cl2, use the following formula: c1 = c2 = 2cl ? (cpin + cp) where: cl is load capacitance stated by crystal manufacturer cpin is the SI51210 pin capacitance (4 pf). cp is the parasitic capacitance of the pcb traces. example: if a crystal with cl = 12 pf specification is used and cp = 1 pf (parasitic pcb capacitance on pcb), 19 or 20 pf external capacitors from pi ns xin (pin 2) and xout (pin 3) to vss are required. us ers must verify cp value. vdd vss xout xin fsel ssclk3 vdd SI51210 0.1 f 10f cl1 cl2 vdd 5k 5k xin xout
SI51210 preliminary rev. 0.7 7 3. functional description 3.1. input frequency range the input frequency range is from 8.0 to 48.0 mhz for crysta ls and ceramic resonators. if an external clock is used, the input frequency range is from 8.0 to 166.0 mhz. 3.2. output freque ncy range and outputs up to two outputs can be programmed as ssclk or refc lk. ssclk output can be synthesized to any value from 3 to 200 mhz with spread based on valid input frequency. the spread at ssclk pins can be stopped by the sson input control pin. if sson pin is high (vdd), the frequency at ssclk pin is synthesized to the nominal value of the input frequency and there is no spread. refclk is the buffered output of the oscillator and is the same frequency as the input frequency without spread. however, refclk_d output is divided by output dividers from 2 to 32. by using only low cost, fundamental mode crystals, the SI51210 can synthesize output frequenc y up to 200 mhz, eliminating the need for higher order crystals (xtals) and crystal oscillators (xos). this redu ces the cost while improvin g the system clock accuracy, performance, and reliability 3.3. programmable modulation frequency the spread spectrum clock (ssc) modulation default valu e is 31.5 khz. the higher values of up to 62 khz can also be programmed. less than 30 khz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio re ceivers within the vicinity. 3.4. programmable spread percent (%) the spread percent (%) value is programmable from 0.25% to 1% (center spread) for all ssclk frequencies. it is possible to program smalle r or larger non-standard va lues of spread percentage. contact silicon labs if these non-standard spread percent values are required in the application. 3.5. sson or frequency select (fsel) the SI51210 pin 4 and 5 can be programmed as either sson to enable or disable the programmed spread percent value or as frequency select (fsel). if sson is used, when this pin is pulled high (vdd), the spread is stopped and the frequency is the nominal value without spread. if low (gnd), the frequency is the nominal value with the spread. if fsel function is used, the output pin can be programme d for different set of frequencies as selected by fsel. ssclk value can be any frequency from 3 to 200 mhz, but the spread % is the same percent value. refclk is the same frequency as the input reference clock and the refclk_d is input clock divided by 2 to 32 without spread . the set of frequencies in table 4 is give n as an example, using a 48 mhz crystal. 3.6. power down (pd ) or output enable (oe) the SI51210 pin 5 can be programmed as pd input. pin 4 and pin 5 can be programmed as oe input. pd turns off both pll and output buffers whereas oe on ly disables the output buffers to hi-z. table 4. example frequencies fsel (pin 4) ssclk1 (pin 5) 066mhz, 1% 133mhz, 1%
SI51210 8 preliminary rev. 0.7 4. pin descriptions: 6-pin tdfn table 5. SI51210 6-pin descriptions pin # name type description 1 vdd pwr 2.5 to 3.3 v power supply. 2 xin/clkin i external crystal and clock input. 3 xout o crystal output. leave this pin unconn ected (floating) if an external clock input is used. 4 ssclk1/refclk/ fsel/ssel/sson / oe2 i/o programmable ssclk1 or refclk output or multifunction control input. the frequency at this pin is synthesized by internal pll if pro- grammed as ssclk1 with or without spread. if programmed as ref- clk, output clock is buffered output of crystal or reference clock input. if programmed as multifunct ion control input, it can be oe, fsel, ssel and sson . 5 ssclk2/refclk_d/ oe1/fsel/ssel/ sson /pd i/o programmable ssclk2 or refclk_d output or multifunction control input. the frequency at this pin is synthesized by internal pll if pro- grammed as ssclk2 with or without spread. if programmed as refclk_d, output clock is buffered output of crystal or reference clock input divided by 2 to 32. if programmed as multifunction control input, it can be oe, pd , fsel, ssel and sson . 6 vss gnd ground. 6 5 4 1 2 3 vss ssclk2/refclk_d fsel/ssel/ sson/pd/oe1 ssclk1/refclk fsel/ssel/ sson/oe2 vdd xout xin/clkin SI51210
SI51210 preliminary rev. 0.7 9 5. ordering information part number package type temperature SI51210-axxxfm 6-pin tdfn commercial, 0 to 70 ? c SI51210-axxxfmr 6-pin tdfn?tape and reel co mmercial, 0 to 70 ? c si 51210 si 51210 programmable clock generator product family axxx fmr a = product revision a 2 nd option code = xxx a three character code will be assigned for each unique configuration . device starts operation upon powerup . operating temp range : f = 0 to + 70 c m = tdfn, rohs6 , pb -free r = tape & reel (blank) = tubes si512xx
SI51210 10 preliminary rev. 0.7 6. package outline: 6-pin tdfn p i n 1 a r e a note pin 1 corner 1 3 1.400.05 1.200.05 0.00-0.05 46 0.200.05 0.400.05 0.400.05 0.750.05 0.200.025
SI51210 preliminary rev. 0.7 11 n otes :
SI51210 12 preliminary rev. 0.7 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brand names mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon labor atories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and specifically di sclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI51210

	To Download SI51210 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .